sram_test Project Status (08/01/2017 - 16:34:34)
Project File: sram_test.xise Parser Errors: No Errors
Module Name: sram_test Implementation State: Programming File Generated
Target Device: xc3s1000-4fg320
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
130 Warnings (100 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 445 15,360 2%  
Number of 4 input LUTs 1,168 15,360 7%  
Number of occupied Slices 790 7,680 10%  
    Number of Slices containing only related logic 790 790 100%  
    Number of Slices containing unrelated logic 0 790 0%  
Total Number of 4 input LUTs 1,318 15,360 8%  
    Number used as logic 1,162      
    Number used as a route-thru 150      
    Number used as Shift registers 6      
Number of bonded IOBs 86 221 38%  
    IOB Flip Flops 18      
Number of RAMB16s 2 24 8%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 3.20      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Aug 1 16:34:09 2017075 Warnings (75 new)13 Infos (13 new)
Translation ReportCurrentTue Aug 1 16:34:15 2017012 Warnings (2 new)0
Map ReportCurrentTue Aug 1 16:34:20 201708 Warnings (8 new)3 Infos (3 new)
Place and Route ReportCurrentTue Aug 1 16:34:31 2017015 Warnings (5 new)0
Power Report     
Post-PAR Static Timing ReportCurrentTue Aug 1 16:34:35 2017020 Warnings (10 new)5 Infos (5 new)
Bitgen ReportCurrentTue Aug 1 16:34:42 2017001 Info (1 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrentTue Aug 1 16:34:42 2017

Date Generated: 08/01/2017 - 16:34:34