Metadata-Version: 2.4
Name: peakrdl-regblock
Version: 1.2.0
Summary: Compile SystemRDL into a SystemVerilog control/status register (CSR) block
Author: Alex Mykyta
License: LGPLv3
Project-URL: Source, https://github.com/SystemRDL/PeakRDL-regblock
Project-URL: Tracker, https://github.com/SystemRDL/PeakRDL-regblock/issues
Project-URL: Changelog, https://github.com/SystemRDL/PeakRDL-regblock/releases
Project-URL: Documentation, https://peakrdl-regblock.readthedocs.io/
Keywords: SystemRDL,PeakRDL,CSR,compiler,tool,registers,generator,Verilog,SystemVerilog,register abstraction layer,FPGA,ASIC
Classifier: Development Status :: 5 - Production/Stable
Classifier: Programming Language :: Python
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3 :: Only
Classifier: Intended Audience :: Developers
Classifier: License :: OSI Approved :: GNU Lesser General Public License v3 (LGPLv3)
Classifier: Operating System :: OS Independent
Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
Requires-Python: >=3.7
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: systemrdl-compiler~=1.29
Requires-Dist: Jinja2>=2.11
Provides-Extra: cli
Requires-Dist: peakrdl-cli>=1.2.3; extra == "cli"
Dynamic: license-file

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# PeakRDL-regblock
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.

For the command line tool, see the [PeakRDL project](https://peakrdl.readthedocs.io).

## Documentation
See the [PeakRDL-regblock Documentation](https://peakrdl-regblock.readthedocs.io) for more details
