Metadata-Version: 2.4
Name: SimplHDL
Version: 0.7.1
Summary: A framework for simulating and implementing HDL designs
Author-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
Maintainer-email: Rasmus Grøndahl Olsen <simplhdl@gmail.com>
License: MIT License
        
        Copyright (c) 2024 SimplHDL
        
        Permission is hereby granted, free of charge, to any person obtaining a copy
        of this software and associated documentation files (the "Software"), to deal
        in the Software without restriction, including without limitation the rights
        to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
        copies of the Software, and to permit persons to whom the Software is
        furnished to do so, subject to the following conditions:
        
        The above copyright notice and this permission notice shall be included in all
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        THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
        IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
        FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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Project-URL: Homepage, https://github.com/SimplHDL
Project-URL: Documentation, https://simplhdl.readthedocs.io/en/latest/
Project-URL: Repository, https://github.com/SimplHDL/simplhdl.git
Project-URL: Issues, https://github.com/SimplHDL/simplhdl/issues
Classifier: Development Status :: 4 - Beta
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.8
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Classifier: Programming Language :: Python :: 3.12
Classifier: Programming Language :: Python :: 3.13
Classifier: Programming Language :: Python :: 3.14
Classifier: Intended Audience :: Developers
Classifier: License :: OSI Approved :: MIT License
Classifier: Operating System :: OS Independent
Requires-Python: >=3.8
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: importlib-resources; python_version < "3.9"
Requires-Dist: pySVModel==0.3.5
Requires-Dist: pyEDAA.ProjectModel==0.4.3
Requires-Dist: pyyaml
Requires-Dist: types-PyYAML
Requires-Dist: argcomplete
Requires-Dist: jinja2
Requires-Dist: GitPython
Requires-Dist: rich
Requires-Dist: vsg
Requires-Dist: flake8
Requires-Dist: black
Requires-Dist: systemrdl-compiler
Requires-Dist: peakrdl-html
Requires-Dist: peakrdl-regblock>=1.2.0
Requires-Dist: peakrdl-pyuvm
Dynamic: license-file

## Introduction

SimplHDL is a plugin-based command-line application for simplifying FPGA and
ASIC development regardless of EDA tools and flows.

The goal is to embrase structured and reusable designs by creating a generic
project model that can be used in any hdl development flow regardless of
project structure and EDA tool requirements.

The plugin based architecture allows for SimplHDL to be migrated into any
existing project, replacing ad-hoc simulation and implmentation scripts while
providing a intuitive command-line interface for HDL design and verification
engineers.

I wide vararity of languges, standards and tools are supported.

### HDL languages

* Verilog / System Verilog
* VHDL
* Chisel
* SystemRDL
* IPXact
* Vivado IP containters (.xci, .xcix)
* Quartus IP containers (.ip)

### Methodologies

* UVM
* OSVMM
* UVVM
* Cocotb
* pyuvm

### EDA Tools

* Vivado
* Quartus
* Modelsim
* Questasim
* Xsim
* Vcs
* Riviera Pro
* Xcelium (coming)
* Verilator (coming)
* Icarus (coming)
* GHDL (coming)

## Getting Started

SimplHDL currently works on Linux and Windows WSL. It is written in Python and can
be installed with *pip*. To run SimplHDL Python 3.8 or later is required. The
tools for the flows you wish to run also need to be installed and set up
correctly in the shell environment. SimplHDL can be installed on your system's
Python installation, but it is highly recommended to install and run SimplHDL
in a Python virtual environment or a Conda environment.

## Example

To quickly try out SimplHDL follow these steps. In this example, we will use
Vivado and QuestaSim. The prerequisites are that SimplHDL install installed and
Vivado and QuestaSim are correctly set up in your shell environment.

1. Clone Git repository from GitHub

```console
git clone https://github.com/SimplHDL/simplhdl.git
```

2. install SimplHDL from source

```console
pip install ./simplhdl
```

3. Run simulation

```console
cd simplhdl/examples/hdl/alu/sim
simpl questasim
```

4. Run simulation interactively in Gui.

```console
cd simplhdl/examples/hdl/alu/sim
simpl questasim --gui
```

5. Run implementation

```console
cd ../syn
simpl vivado
```

6. Run implementation interactively in Gui.

```console
simpl vivado --gui
```

In this example, the project specification is written in Yaml. This format is
only meant as a demonstration. To integrate SimplHDL into your project, you have
to write a parser plugin for your specific project specification format.
See the documentation and plugin examples for more information.

## Links

* Homepage:
* Source: <https://github.com/SimplHDL/simplhdl>
* Tracker: <https://github.com/SimplHDL/simplhdl/issues>
