.gitignore
.gitlab-ci.yml
.pre-commit-config.yaml
AUTHORS
CHANGELOG.md
LICENSE
README.md
availsim4.py
notebook_example_availsim4.ipynb
pyproject.toml
sonar-project.properties
CI/sonar.sh
availsim4.egg-info/PKG-INFO
availsim4.egg-info/SOURCES.txt
availsim4.egg-info/dependency_links.txt
availsim4.egg-info/entry_points.txt
availsim4.egg-info/requires.txt
availsim4.egg-info/top_level.txt
availsim4core/__init__.py
availsim4core/configuration.py
availsim4core/main.py
availsim4core/logging/logging.conf
availsim4core/resources/__init__.py
availsim4core/resources/excel_strings.py
availsim4core/resources/script_templates/__init__.py
availsim4core/resources/script_templates/master_job_template.sh
availsim4core/resources/script_templates/master_submission_template.sub
availsim4core/resources/script_templates/single_job_template.sh
availsim4core/resources/script_templates/single_submission_template.sub
availsim4core/src/__init__.py
availsim4core/src/analysis.py
availsim4core/src/context/__init__.py
availsim4core/src/context/context.py
availsim4core/src/context/phase/__init__.py
availsim4core/src/context/phase/phase.py
availsim4core/src/context/phase/phase_manager.py
availsim4core/src/context/rca/__init__.py
availsim4core/src/context/rca/rca_manager.py
availsim4core/src/context/rca/rca_record.py
availsim4core/src/context/system/__init__.py
availsim4core/src/context/system/architecture_entry.py
availsim4core/src/context/system/failure.py
availsim4core/src/context/system/failure_factory.py
availsim4core/src/context/system/failure_mode.py
availsim4core/src/context/system/failure_mode_assignments.py
availsim4core/src/context/system/inspection.py
availsim4core/src/context/system/minimal_replaceable_unit.py
availsim4core/src/context/system/phase_jump_trigger.py
availsim4core/src/context/system/rca_trigger.py
availsim4core/src/context/system/sanity_check.py
availsim4core/src/context/system/system_element.py
availsim4core/src/context/system/system_template.py
availsim4core/src/context/system/system_utils.py
availsim4core/src/context/system/children_logic/__init__.py
availsim4core/src/context/system/children_logic/and_.py
availsim4core/src/context/system/children_logic/children_logic.py
availsim4core/src/context/system/children_logic/children_logic_factory.py
availsim4core/src/context/system/children_logic/oo.py
availsim4core/src/context/system/children_logic/required_component.py
availsim4core/src/context/system/children_logic/tolerated_fault.py
availsim4core/src/context/system/component_tree/__init__.py
availsim4core/src/context/system/component_tree/basic.py
availsim4core/src/context/system/component_tree/component.py
availsim4core/src/context/system/component_tree/component_factory.py
availsim4core/src/context/system/component_tree/compound.py
availsim4core/src/context/system/component_tree/status.py
availsim4core/src/context/system/probability_law/__init__.py
availsim4core/src/context/system/probability_law/binomial_law.py
availsim4core/src/context/system/probability_law/deterministic_law.py
availsim4core/src/context/system/probability_law/exponential_law.py
availsim4core/src/context/system/probability_law/exponentiated_weibull_law.py
availsim4core/src/context/system/probability_law/normal_law.py
availsim4core/src/context/system/probability_law/probability_law.py
availsim4core/src/context/system/probability_law/probability_law_factory.py
availsim4core/src/context/system/probability_law/weibull_law.py
availsim4core/src/discrete_event_simulation/__init__.py
availsim4core/src/discrete_event_simulation/b_event_generator.py
availsim4core/src/discrete_event_simulation/c_event_generator.py
availsim4core/src/discrete_event_simulation/discrete_event_simulation.py
availsim4core/src/discrete_event_simulation/event/__init__.py
availsim4core/src/discrete_event_simulation/event/event.py
availsim4core/src/discrete_event_simulation/event/b_event/__init__.py
availsim4core/src/discrete_event_simulation/event/b_event/b_event.py
availsim4core/src/discrete_event_simulation/event/b_event/basic_b_event.py
availsim4core/src/discrete_event_simulation/event/b_event/failure_event/__init__.py
availsim4core/src/discrete_event_simulation/event/b_event/failure_event/blind_failure_event.py
availsim4core/src/discrete_event_simulation/event/b_event/failure_event/detectable_failure_event.py
availsim4core/src/discrete_event_simulation/event/b_event/failure_event/failure_event.py
availsim4core/src/discrete_event_simulation/event/b_event/failure_event/failure_event_factory.py
availsim4core/src/discrete_event_simulation/event/b_event/held_event/__init__.py
availsim4core/src/discrete_event_simulation/event/b_event/held_event/end_holding_event.py
availsim4core/src/discrete_event_simulation/event/b_event/inspection_event/__init__.py
availsim4core/src/discrete_event_simulation/event/b_event/inspection_event/end_inspection_event.py
availsim4core/src/discrete_event_simulation/event/b_event/inspection_event/inspection_event_factory.py
availsim4core/src/discrete_event_simulation/event/b_event/inspection_event/start_inspection_event.py
availsim4core/src/discrete_event_simulation/event/b_event/phase_event/__init__.py
availsim4core/src/discrete_event_simulation/event/b_event/phase_event/jump_phase_event.py
availsim4core/src/discrete_event_simulation/event/b_event/phase_event/next_phase_event.py
availsim4core/src/discrete_event_simulation/event/b_event/phase_event/next_phase_if_failure_event.py
availsim4core/src/discrete_event_simulation/event/b_event/repair_event/__init__.py
availsim4core/src/discrete_event_simulation/event/b_event/repair_event/end_repairing_event.py
availsim4core/src/discrete_event_simulation/event/b_event/repair_event/minimal_replaceable_unit_end_repairing_event.py
availsim4core/src/discrete_event_simulation/event/b_event/repair_event/minimal_replaceable_unit_start_repairing_event.py
availsim4core/src/discrete_event_simulation/event/b_event/repair_event/start_repairing_event.py
availsim4core/src/discrete_event_simulation/event/c_event/__init__.py
availsim4core/src/discrete_event_simulation/event/c_event/c_event.py
availsim4core/src/discrete_event_simulation/event/c_event/component_c_event.py
availsim4core/src/discrete_event_simulation/event/c_event/postpone_c_event.py
availsim4core/src/discrete_event_simulation/event/c_event/failure_event/__init__.py
availsim4core/src/discrete_event_simulation/event/c_event/failure_event/order_failure_event.py
availsim4core/src/discrete_event_simulation/event/c_event/failure_event/reevaluate_order_all_failure_event.py
availsim4core/src/discrete_event_simulation/event/c_event/held_event/__init__.py
availsim4core/src/discrete_event_simulation/event/c_event/held_event/order_end_holding_event.py
availsim4core/src/discrete_event_simulation/event/c_event/inspection_event/__init__.py
availsim4core/src/discrete_event_simulation/event/c_event/inspection_event/order_end_inspection_event.py
availsim4core/src/discrete_event_simulation/event/c_event/inspection_event/order_start_inspection_event.py
availsim4core/src/discrete_event_simulation/event/c_event/inspection_event/reevaluate_order_all_inspection_event.py
availsim4core/src/discrete_event_simulation/event/c_event/phase_event/__init__.py
availsim4core/src/discrete_event_simulation/event/c_event/phase_event/order_jump_phase_event.py
availsim4core/src/discrete_event_simulation/event/c_event/phase_event/order_next_phase_event.py
availsim4core/src/discrete_event_simulation/event/c_event/phase_event/order_next_phase_if_failure_event.py
availsim4core/src/discrete_event_simulation/event/c_event/repair_event/__init__.py
availsim4core/src/discrete_event_simulation/event/c_event/repair_event/minimal_replaceable_unit_order_repair_event.py
availsim4core/src/discrete_event_simulation/event/c_event/repair_event/order_repair_event.py
availsim4core/src/exporter/__init__.py
availsim4core/src/exporter/export_manager.py
availsim4core/src/exporter/exporter.py
availsim4core/src/exporter/graph_exporter.py
availsim4core/src/exporter/input_file_exporter.py
availsim4core/src/exporter/xlsx/__init__.py
availsim4core/src/exporter/xlsx/xlsx_exporter.py
availsim4core/src/exporter/xlsx/analysis/__init__.py
availsim4core/src/exporter/xlsx/analysis/xlsx_analysis_exporter.py
availsim4core/src/exporter/xlsx/analysis/xlsx_component_listing.py
availsim4core/src/exporter/xlsx/analysis/xlsx_component_tree_extented.py
availsim4core/src/exporter/xlsx/analysis/xlsx_component_tree_simple.py
availsim4core/src/exporter/xlsx/analysis/xlsx_connectivity_matrix.py
availsim4core/src/exporter/xlsx/analysis/xlsx_critical_failure_paths.py
availsim4core/src/exporter/xlsx/result/__init__.py
availsim4core/src/exporter/xlsx/result/xlsx_execution_metrics.py
availsim4core/src/exporter/xlsx/result/xlsx_last_timeline.py
availsim4core/src/exporter/xlsx/result/xlsx_rca.py
availsim4core/src/exporter/xlsx/result/xlsx_summary.py
availsim4core/src/reader/__init__.py
availsim4core/src/reader/reader.py
availsim4core/src/reader/xlsx/__init__.py
availsim4core/src/reader/xlsx/monte_carlo_reader.py
availsim4core/src/reader/xlsx/quasi_monte_carlo_reader.py
availsim4core/src/reader/xlsx/sensitivity_analysis_reader.py
availsim4core/src/reader/xlsx/simulation_reader.py
availsim4core/src/reader/xlsx/splitting_monte_carlo_reader.py
availsim4core/src/reader/xlsx/system_template_reader.py
availsim4core/src/reader/xlsx/xlsx_utils.py
availsim4core/src/reader/xlsx/system_template/__init__.py
availsim4core/src/reader/xlsx/system_template/architecture_sheet_reader.py
availsim4core/src/reader/xlsx/system_template/failure_mode_assignments_sheet_reader.py
availsim4core/src/reader/xlsx/system_template/failure_modes_sheet_reader.py
availsim4core/src/reader/xlsx/system_template/inspection_sheet_reader.py
availsim4core/src/reader/xlsx/system_template/mru_sheet_reader.py
availsim4core/src/reader/xlsx/system_template/phase_jump_triggers_sheet_reader.py
availsim4core/src/reader/xlsx/system_template/phases_sheet_reader.py
availsim4core/src/reader/xlsx/system_template/root_cause_analysis_triggers_sheet_reader.py
availsim4core/src/reader/xlsx/system_template/sheet_reader.py
availsim4core/src/results/__init__.py
availsim4core/src/results/result_record_entry.py
availsim4core/src/results/result_record_entry_component.py
availsim4core/src/results/result_record_entry_phase.py
availsim4core/src/results/results.py
availsim4core/src/results/simulation_results.py
availsim4core/src/runner/__init__.py
availsim4core/src/runner/htcondor_runner.py
availsim4core/src/runner/local_runner.py
availsim4core/src/sensitivity_analysis/__init__.py
availsim4core/src/sensitivity_analysis/exploration_strategy.py
availsim4core/src/sensitivity_analysis/exploration_strategy_factory.py
availsim4core/src/sensitivity_analysis/sensitivity_analysis.py
availsim4core/src/sensitivity_analysis/system_modifier/__init__.py
availsim4core/src/sensitivity_analysis/system_modifier/system_modifier.py
availsim4core/src/sensitivity_analysis/system_modifier/system_modifier_combination.py
availsim4core/src/sensitivity_analysis/system_modifier/system_modifier_combination_inner_strategy.py
availsim4core/src/sensitivity_analysis/system_modifier/system_modifier_combination_outer_strategy.py
availsim4core/src/sensitivity_analysis/system_modifier/system_modifier_combination_random_factory.py
availsim4core/src/sensitivity_analysis/system_modifier/system_modifier_combination_strategy.py
availsim4core/src/sensitivity_analysis/system_modifier/system_modifier_combination_strategy_director.py
availsim4core/src/sensitivity_analysis/system_modifier/system_modifier_combination_zip_strategy.py
availsim4core/src/simulation/__init__.py
availsim4core/src/simulation/monte_carlo.py
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availsim4core/src/simulation/quick_parse.py
availsim4core/src/simulation/simulation.py
availsim4core/src/simulation/splitting_mc.py
availsim4core/src/simulation/splitting_mc_matrix.py
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availsim4core/src/simulation/des_random_generator/des_random_generator.py
availsim4core/src/simulation/des_random_generator/quasi_monte_carlo_generator.py
availsim4core/src/simulation/importance_splitting/__init__.py
availsim4core/src/simulation/importance_splitting/simple_weights.py
availsim4core/src/simulation/importance_splitting/weights.py
availsim4core/src/statistics/__init__.py
availsim4core/src/statistics/critical_failure_paths.py
availsim4core/src/statistics/statistics.py
availsim4core/src/timeline/__init__.py
availsim4core/src/timeline/record.py
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availsim4core/test/E2E/E2E_utils.py
availsim4core/test/E2E/__init__.py
availsim4core/test/E2E/test_E2E_Benchmark.py
availsim4core/test/E2E/test_E2E_Inspection.py
availsim4core/test/E2E/test_E2E_MRU.py
availsim4core/test/E2E/test_E2E_RCA.py
availsim4core/test/E2E/test_E2E_children_logic.py
availsim4core/test/E2E/test_E2E_convergence_rare_event.py
availsim4core/test/E2E/test_E2E_custom_children_logic.py
availsim4core/test/E2E/test_E2E_failure_on_demand.py
availsim4core/test/E2E/test_E2E_fancy_exporter.py
availsim4core/test/E2E/test_E2E_held.py
availsim4core/test/E2E/test_E2E_multiple_failure_modes.py
availsim4core/test/E2E/test_E2E_phase_jump.py
availsim4core/test/E2E/test_E2E_phases.py
availsim4core/test/E2E/test_E2E_probabilityFailure.py
availsim4core/test/E2E/test_E2E_quasi_monte_carlo.py
availsim4core/test/E2E/test_E2E_repair.py
availsim4core/test/E2E/test_E2E_sharedChild.py
availsim4core/test/E2E/test_E2E_template.py
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availsim4core/test/E2E/input/fancy_exporter/theoretical_tree.png
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availsim4core/test/E2E/input/phase_jump/phase_jump_inifinite_loop_test.xlsx
availsim4core/test/E2E/input/phase_jump/simulation.xlsx
availsim4core/test/E2E/input/phases/failure_in_each_Phase_but_change_phase_before_failure_system.xlsx
availsim4core/test/E2E/input/phases/never_passing_in_faulty_phase_system.xlsx
availsim4core/test/E2E/input/phases/no_sufficient_time_in_faulty_phase_system.xlsx
availsim4core/test/E2E/input/phases/option_on_timing__after_failure__system.xlsx
availsim4core/test/E2E/input/phases/option_on_timing__after_repair__system.xlsx
availsim4core/test/E2E/input/phases/option_on_timing_v2__after_repair__system.xlsx
availsim4core/test/E2E/input/phases/option_on_timing_v2__never__system.xlsx
availsim4core/test/E2E/input/phases/passing_once_in_faulty_phase_system.xlsx
availsim4core/test/E2E/input/phases/simulation.xlsx
availsim4core/test/E2E/input/phases/sufficient_time_in_faulty_phase_system.xlsx
availsim4core/test/E2E/input/phases/sufficient_time_in_faulty_phase_v2_system.xlsx
availsim4core/test/E2E/input/phases/version1_no_phase_system.xlsx
availsim4core/test/E2E/input/phases/version2_failure_in_each_phase_system.xlsx
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availsim4core/test/E2E/input/phases/version2_failure_in_each_phase_v3_system.xlsx
availsim4core/test/E2E/input/phases/version3_failure_in_each_phase_2_failure_modes_system.xlsx
availsim4core/test/E2E/input/phases/version3_failure_in_each_phase_2_failure_modes_v2_system.xlsx
availsim4core/test/E2E/input/phases/version4_check_postpone_v1_system.xlsx
availsim4core/test/E2E/input/phases/version4_check_postpone_v2_system.xlsx
availsim4core/test/E2E/input/phases/version4_check_postpone_v3_system.xlsx
availsim4core/test/E2E/input/phases/version4_phases_but_no_failures_system.xlsx
availsim4core/test/E2E/input/phases/version5_phaseSpecificToFailureMode_parallelFault1_system.xlsx
availsim4core/test/E2E/input/phases/version5_phaseSpecificToFailureMode_parallelFault2_system.xlsx
availsim4core/test/E2E/input/phases/version5_phaseSpecificToFailureMode_parallelFault3_system.xlsx
availsim4core/test/E2E/input/phases/version5_phaseSpecificToFailureMode_parallelFault4_system.xlsx
availsim4core/test/E2E/input/phases/version5_phase_specific_to_failure_mode_system.xlsx
availsim4core/test/E2E/input/repair/testRepair_scenario_1_system.xlsx
availsim4core/test/E2E/input/repair/testRepair_scenario_2_system.xlsx
availsim4core/test/E2E/input/repair/testRepair_simulation.xlsx
availsim4core/test/E2E/input/shared_child/shared_child1_system.xlsx
availsim4core/test/E2E/input/shared_child/shared_child_simulation.xlsx
availsim4core/test/E2E/input/template/simulation.xlsx
availsim4core/test/E2E/input/template/system.xlsx
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availsim4core/test/unit/context/__init__.py
availsim4core/test/unit/context/test_PhaseManager.py
availsim4core/test/unit/context/system/__init__.py
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availsim4core/test/unit/context/system/test_ComponentFactory.py
availsim4core/test/unit/context/system/test_Compound.py
availsim4core/test/unit/context/system/test_FailureFactory.py
availsim4core/test/unit/context/system/test_FailureMode.py
availsim4core/test/unit/context/system/test_MinimalReplaceableUnit.py
availsim4core/test/unit/context/system/test_SystemUtils.py
availsim4core/test/unit/context/system/children_logic/__init__.py
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availsim4core/test/unit/context/system/probability_law/test_probabilityLawFactory.py
availsim4core/test/unit/discrete_event_simulation/__init__.py
availsim4core/test/unit/discrete_event_simulation/test_BEventGenerator.py
availsim4core/test/unit/discrete_event_simulation/test_CEventGenerator.py
availsim4core/test/unit/discrete_event_simulation/test_DiscreteEventSimulation.py
availsim4core/test/unit/discrete_event_simulation/event/__init__.py
availsim4core/test/unit/discrete_event_simulation/event/test_Event.py
availsim4core/test/unit/discrete_event_simulation/event/b_event/__init__.py
availsim4core/test/unit/discrete_event_simulation/event/b_event/failure_event/__init__.py
availsim4core/test/unit/discrete_event_simulation/event/b_event/failure_event/test_FailureEventFactory.py
availsim4core/test/unit/exporter/__init__.py
availsim4core/test/unit/exporter/model_output_regenerate_system_template.xlsx
availsim4core/test/unit/exporter/test_XlsxAnalysisExporter.py
availsim4core/test/unit/reader/__init__.py
availsim4core/test/unit/reader/test_MonteCarlorReader.py
availsim4core/test/unit/reader/test_SensitivityAnalysisReader.py
availsim4core/test/unit/reader/test_SimulationReader.py
availsim4core/test/unit/reader/test_SystemTemplateReader.py
availsim4core/test/unit/reader/test_XlsxReader.py
availsim4core/test/unit/results/__init__.py
availsim4core/test/unit/results/test_SimulationResults.py
availsim4core/test/unit/runner/__init__.py
availsim4core/test/unit/runner/test_HTCondorRunner.py
availsim4core/test/unit/sensitivity_analysis/__init__.py
availsim4core/test/unit/sensitivity_analysis/test_ExplorationStrategyFactory.py
availsim4core/test/unit/sensitivity_analysis/test_SensitivityAnalysis.py
availsim4core/test/unit/sensitivity_analysis/system_modifier/__init__.py
availsim4core/test/unit/sensitivity_analysis/system_modifier/test_SystemModifierCombinationInnerStrategy.py
availsim4core/test/unit/sensitivity_analysis/system_modifier/test_SystemModifierCombinationOuterStrategy.py
availsim4core/test/unit/sensitivity_analysis/system_modifier/test_SystemModifierCombinationStrategy.py
availsim4core/test/unit/sensitivity_analysis/system_modifier/test_SystemModifierCombinationStrategyDirector.py
availsim4core/test/unit/simulation/__init__.py
availsim4core/test/unit/simulation/generators/__init__.py
availsim4core/test/unit/simulation/generators/test_QuasiMonteCarloGenerator.py
availsim4core/test/unit/statistics/__init__.py
availsim4core/test/unit/timeline/__init__.py
availsim4core/test/unit/timeline/test_RecordGenerator.py
availsim4core/test/unit/timeline/test_Timeline.py
doc/AVS4_10.png
doc/UML/AvailSim4ClassUML.xml
doc/UML/src.uml
doc/specification/AvailSim4Spec.md
doc/specification/figures/Existing-CERN-accelerator-complex.png
doc/specification/figures/IT_small.jpg
doc/specification/figures/MRU_lca_root.png
doc/specification/figures/MRU_lca_sec.png
doc/specification/figures/MRU_map.png
doc/specification/figures/UML_AvailSim4.png
doc/specification/figures/cardio.png
doc/specification/figures/chart_DES.png
doc/specification/figures/durationOfSimulations.png
doc/specification/figures/notShared.png
doc/specification/figures/phases.png
doc/specification/figures/rootShared.png
doc/specification/figures/secShared.png
doc/specification/figures/sensitivityAnalysis.png
doc/specification/figures/simpleTimeLine.png
doc/specification/figures/structureByObject.png
doc/specification/figures/structureByVariable.png
doc/specification/figures/systemDescription.png
doc/specification/figures/timelines.png
doc/user_guide/developer_guide.md
doc/user_guide/user_guide.md
doc/user_guide/figures/MRU_lca_root.png
doc/user_guide/figures/MRU_lca_sec.png
doc/user_guide/figures/MRU_map.png
doc/user_guide/figures/chart_DES.png
doc/user_guide/figures/example_of_ARCHITECTURE_sheet.png
doc/user_guide/figures/notShared.png
doc/user_guide/figures/rootShared.png
doc/user_guide/figures/secShared.png
doc/user_guide/figures/simpleTimeLine.png
doc/user_guide/figures/simple_phases_timeline.png
doc/user_guide/figures/systemDescription.png
input_template/simulation.xlsx
input_template/system.xlsx